PORTFOLIO

Aim of the project is the definition of hardware/software solutions for achieving higher security on mobile systems with cost and power consumption constraints. The project, involving cooperation between USI and SUPSI, deals with innovative efficient and comprehensive security policies for mobile systems design. The finally defined policy will be validated by means of a physical demonstrator (implemented partly as software, partly by means of fast-prototyping technologies) that could be the initial step for an industrial prototype.

Security is one increasingly important problem in a world where the internet-based solutions for such diverse environments as banking, commerce, health-care, public administration etc. are ever growing. In particular, the widespread use of mobile systems (from the simplest ones, smart-card, to palm held devices, 3G phones etc) poses new challenges to the problem of granting and managing security. In fact security in a “pervasive computing” environment may become one of the main pitfalls against further spreading of ICT in daily life. Project “Mobile Security” affords the problem in global terms, considering the various critical points from hardware to operating system and to interface with computer networks.
The project will reinforce the strong cooperation between the two institutions: as a consequence the already present expertise will be further strengthened by creating a joint “competence center” on Security, a key resource for the stakeholders of the Swiss Economy, with a specific interest in mobile security, like banks.

We briefly describe here the work that has been done at ALaRI within the context of the project for Gebert Rüf Foundation. The preliminary study of cryptographic algorithms is completed and a C implementation of both the Advanced Encryption Standard (AES) and the Elliptic Curves Cryptosystem (ECC) has been produced and functionally tested. This implementation adheres to the various cryptographic standards specifications published by the NIST institution. Moreover, a paper describing an efficient implementation of the AES is to be presented at the CHES 2002 Workshop, and the same algorithm has been coded and optimised for two embedded platforms, the Intel Strongarm processor (SA-1110 board) and the ST Lx VLIW core. Last, a study of the security features of the Linux OS on Strongarm has been developed, and an extension of the Kernel has been produced which uses the AES cryptographic services within the filesystem.
After the first phase of research focused in particular on the security algorithms and on optimum choices for the Hardware/Software modules, including conceptual design of special-purpose hardware units, in the second phase of the Mobile Security project attention was given in particular to testing issues.
The problem of testing is quite complex and involves dealing with the system at different levels of abstraction, such as:
- The networking layer. Throughout the second phase, the networking protocol IPSec was modelled through the Unified Modelling Language (UML). This model has lead to a generation of test sequences to be applied to the scheme; the work still needs to be completed, but the general methodology has been put in place.
- The Operating System layer. eCOS, an operating system particularly suited to mobile system applications (that was ported on the StrongArm development boards used for the experimental phases carried out at ALaRI), was chosen and analyzed; this phase has led to the development of the security layer and to the security-related testing methodology that can be used for the whole system.
- The security layer. In order to make the dedicated hardware accessible to all applications, a security layer between the IP network layer and the device driver is needed. The Lightweight TCP/IP stack lwIP was taken as a starting point and expanded to include security features. It is felt that the choice of a lightweight protocol can help enhancing the testability of the system.
Simultaneously, further research was developed with reference to the design of dedicated hardware modules, as the presence of hardware accelerators is beneficial for the performances of the whole system. The novel hash function family SHA-2 has been taken into consideration, and a thorough study of a SHA-2 hardware core has been carried out (taking processing speed as a primary goal).
The chosen hardware-software platform was adopted as a reference for integration and evaluation of the cryptographic hardware developed by SUPSI. In particular, hardware development concentrated on a co-processor implementing the Advanced Encryption Standard (Rijndael) algorithm, as it was felt that this would be the most intensively used.
Activities were organized along the following steps:
- simulation and optimization of hardware modules
- design specification of the complete test suite
- system integration with test application and benchmarking capabilities
Hardware design and development was accompanied by development of the suitable software segments (drivers) allowing final integration of the coprocessor on the development board.
Original research performed by ALaRI within the project has led to the publications listed below.

G. Bertoni, L. Breveglieri, P. Fragneto, M. Macchetti, S. Marchesin, “Efficient Software Implementation of AES on 32-bits Platforms”, proceedings of CHES 2002 , page(s) 159-171, Redwood Shores, August 13-15 2002.
K. Atasu, L. Breveglieri, M. Macchetti, “Efficient AES Implementations for ARM Based Platforms”, proceedings of SAC 2004, vol. 1, page(s) 841-845, Nicosia, 14-17 March 2004.
A. Bircan, G. Bertoni, L. Breveglieri, P. Fragneto, M. Macchetti, V. Zaccaria, “About the Performances of the Advanced Encryption Standard in Embedded Systems with Cache Memory”, proceedings of ISCAS 2003, vol. 5, page(s) 145-148, Bangkok, May 25-28 2003.
L. Dadda, M. Macchetti, J. Owen, “The Design of a High-Speed ASIC Unit for the Hash Function SHA-256 (384,512)”, proceedings of DATE 2004, vol. 3, page(s) 70-75, Paris, 16-20 February 2004.
S. Chakrabarti, L. Dadda, M.Macchetti, J. Owen, “An ASIC Design for a High Speed Implementation of the Hash Function SHA-256 (384, 512)”, proceedings of GLSVLSI 2004, page(s) 421-425, Boston, 26-28 April 2004.

Articles in various journals